Delay calculation

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Delay calculation is the term used in integrated circuit design for the calculation of the delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.

There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required:

Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method.
Two dimensional tables are commonly used in applications such as logic synthesis, placement and routing. These tables take an output load and input slope, and generate a circuit delay and output slope.
A very simple model called the K-factor model is sometimes used. This approximates the delay as a constant plus k times the load capacitance.
Logical effort provides a simple delay calculation that accounts for gate sizing and is analytically tractible.

Similarly there are many ways to calculate the delay of a wire. Note that the delay of a wire will normally be different to each destination. In order of increasing accuracy (and decreasing speed), the most common methods are:

Lumped C. The entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored.
Elmore delay is a simple approximation, often used where speed of calculation is important but the delay through the wire itself cannot be ignored. It uses the R and C values of the wire segments in a simple calculation. The delay of each wire segment is the R of that segment times the downstream C. Then all delays are summed from the root.
Padé approximations, also call moment matching, are more complex methods analytic methods. The oldest of such methods was AWE, with PRIMA and PVL as more recent and sophisticated variants. These methods are faster than circuit simulation and more accurate than Elmore.
Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method.

The delay may also depend on the behaviour of the neighboring nets. This is one of the main effects that is analyzed during signal integrity checks.

References

W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, January 1948, Volume 19, Issue 1, pp. 55-63.

Pillage, L.T.; Rohrer, R.A., Asymptotic waveform evaluation for timing analysis, IEEE Transactions on the Computer-Aided Design of Integrated Circuits and Systems, Volume 9, Issue 4, April 1990, pp. 352 - 366.

Odabasioglu, A.; Celik, M.; Pileggi, L.T., PRIMA: passive reduced-order interconnect macromodeling algorithm, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17, Issue 8, Aug. 1998, pp. 645 - 654

Delay calculation

References

See also