EAsic

The main feature represents the programmability of the logic cells of the IC. The routability inside the chip is not programmable and done via jumpers using a single late stage metal via-mask or alternatively using maskless eBeam Direct-write method. The benefits of this approach over traditional standard cell ASIC design is that the customization is performed by a combination of programming the logic through a bit stream and the interconnect through the via. This means that no custom masks need to be generated. This is now a huge saving and gets even better with newer technologies. In addition the fact that the metal interconnect is essentially standard. That is, very regular means that "back end" processing to analyze for IR drop, crosstalk etc. does not need to be performed. This speeds up the design flow. The direct write e-Beam means there is no minimum order quantities either. The disadvantages of this approach are that if a product is going onto very high volume then it is more cost effective to pay the upfront cost of ASIC and still use standard cell ASIC. Standard cell ASIC is probably half the price of the equivalent eASIC chip. If the product needs to be electrically programmable such as development systems then the only product to use is conventional FPGA. Based on comparisons and quotes the eASIC chip is 2 to 10 times cheaper than FPGA due to a smaller die size and cheaper packages. The power saving compared to FPGA is probably 10 to 20 times lower power. The standard cell ASIC is higher performance and probably 80% the power of the equivalent eASIC Other products in this category come from LSI Logic, NEC Electronics, Altera

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