Front side bus
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In computers, the front side bus (FSB) is a term for the physical bi-directional data bus that carries all electronic signal information between the central processing unit (CPU) and other devices within the system such as random access memory (RAM), the memory containing the system BIOS, AGP video cards, PCI expansion cards, hard disks, etc.
Some computers have an L2 or L3 memory cache external to the CPU connected via a back side bus. This bus and the cache memory connected to it is faster than accessing the system RAM via the front side bus.
Current usage
Most modern front side buses serve as a backbone between the CPU and a chipset. This chipset (usually a combination of a northbridge and a southbridge) is the connection point for all other buses in the system. The PCI, AGP, and memory buses all connect to the chipset to allow for data to flow between the connected devices.These secondary system buses usually run at speeds derived from the front side bus' speed. In general, a faster front side bus means higher processing speeds and a faster computer for a number of reasons which are outlined below.
Related Component Speeds
CPU
The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front side bus (FSB) speed. For example, a processor running at 550 MHz might be using a 100 MHz FSB. This means there is an internal clock multiplier setting of 5.5; the CPU is set to run at 5.5 times frequency of the front side bus: 100 MHz x 5.5 = 550 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved.Memory
Setting a FSB speed is related directly to the speed grade of memory that a system must use. The memory bus connects the northbridge and RAM, just as the frontside bus connects the CPU and northbridge. Often, these two buses must operate at the same frequency. Pushing the front-side bus to 170 MHz means pushing the memory to 170 MHz in most cases.In newer systems, it is possible to see memory ratios of "5:4" and the like. The bus will run 5/4 faster than the memory in this situation, meaning a 200 MHz bus can run with the memory at only 160 MHz. With bus speeds increasing rapidly, it may be necessary to run the RAM at a lower frequency than the system bus in order to stay within the limitations of the DRAM modules on the memory stick. This incurs a performance penalty, but it allows slower RAM to be used with the faster bus speeds that some processors were designed for.
In complex image, audio, video, gaming, and scientific applications where the data set is large, FSB speed becomes a major performance issue. A slow FSB will cause the CPU to spend significant amounts of time waiting for data to arrive from system memory.
Peripheral Buses
Similar to the memory bus, the PCI and AGP buses can also be run asynchronously from the front side bus. In older systems, these buses operated at a set fraction of the frontside bus frequency. This fraction was set by the BIOS, and it depended on the frontside bus speed to an extent as the intended speeds for the buses are 33 MHz for PCI and 66 MHz for AGP.In newer systems the PCI, AGP, and PCI Express peripheral buses often receive their own clock signals, which eliminates their dependence on the frontside bus for timing.
Overclocking
Overclocking is the practice of making computer components operate beyond their stock performance levels.Most motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings. Many CPU manufacturers now "lock" a preset multiplier setting into the chip. It is possible to unlock some locked CPUs; for instance, some Athlons can be unlocked by connecting electrical contacts across points on the CPU's surface. For all processors, increasing the FSB speed can be done to boost processing speed.
This practice does push components beyond their specifications and may cause erratic behavior or premature failure.
Some sample FSB frequencies and bandwidths
| Processor Class | FSB Frequency | FSB Type | Theoretical Bandwidth |
|---|---|---|---|
| Pentium II | 66/100 MHz | GTL+ | 533/800 MB/s |
| Pentium III | 100/133 MHz | GTL+ | 800/1066 MB/s |
| Pentium 4* | 100/133/200 MHz | AGTL+ | 3200/4266/6400 MB/s |
| Pentium M* | 100/133 MHz | AGTL+ | 3200/4266 MB/s |
| Pentium D* | 133/200 MHz | AGTL+ | 4266/6400 MB/s |
| Pentium 4 EE* | 200/266 MHz | AGTL+ | 6400/8533 MB/s |
| Intel Core* | 133/166 MHz | AGTL+ | 4266/5333 MB/s |
| Intel Core 2* | 200/266 MHz | AGTL+ | 6400/8533 MB/s |
| Xeon - P6 core | 100/133 MHz | GTL+ | 800/1066 MB/s |
| Xeon* - Netburst core | 100/133/166/200/266 MHz | AGTL+ | 3200/4266/5333/6400/8533 MB/s |
| Athlon** | 100/133 MHz | EV6 | 1600/2133 MB/s |
| Athlon XP** | 133/166/200 MHz | EV6 | 2133/2666/3200 MB/s |
| Athlon 64/FX/Opteron*** | 600/800/1000 MHz | Hypertransport | 7500/12800/14400 MB/s |
| PowerPC 970 | 900/1000/1250 MHz | Elastic | 7200/8000/10000 MB/s |
| Notes: * - Pentium 4, Pentium M, Pentium D, Pentium EE, Xeon, Intel Core, and Intel Core 2 processors use a front side bus that transfers data four times per cycle ** - Athlon and Athlon XP processors use a front side bus that transfers data twice per cycle (Double data rate) *** - Athlon 64, FX, and Opteron processors have a memory controller on the CPU die, which replaces the traditional FSB. The bus specifications given here are for the HyperTransport link and memory bandwidth. | |||
History
The frontside bus has been a part of computer architecture since applications first started using more memory than a CPU (a very complex integrated circuit) could reasonably hold.The front side bus as it is traditionally known may be disappearing. Originally, this bus was a central connecting point for all system devices and the CPU. However, in recent years this has been breaking down with increasing use of individual point-to-point buses.
Three recent bus technologies are GTL+, EV6, and HyperTransport. Each bus is unique in how it moves data within the system between the CPU and devices.
GTL+/AGTL+ Bus
- Designed by Intel for the Pentium Pro, Pentium II, and Pentium III CPUs, as well as Xeons based on these cores (GTL+)
- Redesigned for the Pentium 4 as well as Xeons on the same cores (AGTL+)
- So-called because it uses GTL+ signalling
- VIA's C3, C7, and Epia CPUs use these buses and are often interchangeable with Intel CPUs
- A "shared" bus, meaning that all CPUs compete over the same physical connection for the bus' bandwidth.
- Designed by DEC (now part of HP) for use with their Alpha EV6 CPUs
- Licensed by AMD for their Athlon and Athlon XP line of CPUs
- A point-to-point protocol connecting each CPU to the northbridge, meaning that each CPU has a dedicated connection to the device.
- Designed largely by AMD in conjunction with the HyperTransport Consortium
- A point-to-point serial connction used by AMD for their Athlon 64, Athlon FX, Athlon X2, and Opteron processors.
- Not technically a front side bus.
- The HyperTransport connection connects AMD CPUs to the rest of the system. Also, these CPUs use it as the baseline to which the internal clock multiplier is applied. Both of these functions were traditionally performed by the frontside bus. On AMD-64 CPUs, the frontside bus, which connects the CPU to the northbridge, has been removed in favor of an on-die memory controller which communicates with RAM directly.
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